The present invention relates to apparatus and methods for an improved CMOS circuit. More particularly, the present invention relates to a new type of CMOS circuit that advantageously reduces the capacitive loading on a common clock, the instantaneous peak current, as well as power consumption, and offers greater speed and performance.
CMOS technology has long been employed to reduce power dissipation. The low impedance gate output to Vss via the n-channel device and the similar low impedance gate output to Vdd via the p-channel device has made CMOS the technology of choice for lower power dissipation in high speed products. However, the complementary nature of CMOS circuits requires a p-channel device and an n-channel device, or two devices, for each input gate. In the aggregate, the high number of devices required to build a CMOS circuit necessitates a large silicon area, increases the capacitive loading on gates, and adversely affects the overall operational speed and performance of the circuit.
A type of clocked logic circuits, commonly known as domino logic, offers speed and area advantages over static CMOS technology while retaining the desirable low power dissipation feature. See, e.g., R. H. Krambeck, et al., "High-Speed Compact Circuits with CMOS," IEEE Journal of Solid State Circuits (June 1982) SC-17(3):614-619. Domino logic gates use either p-channel devices or n-channel devices for evaluating and realizing a Boolean function. Compared to CMOS circuits, domino logic reduces the number of devices required to implement a particular function by approximately half. Concomitantly, capacitive loading and circuit size are significantly reduced.
FIG. 1 shows a typical prior art domino logic stage. Referring to FIG. 1, a single domino logic circuit stage 2 includes a dynamic section comprising devices 10, 12, 14, 16 and 18, and a static inverting buffer 20. P-channel precharge device 10 and n-channel discharge device 18 are clocked by a CLK signal 22. A plurality of input signals A-C on conductors 24, 26, and 28 are respectively coupled to n-channel devices 12, 14, and 16 to form an evaluation tree comprising a pull-down network for realizing an arbitrary combinational function. Since the evaluation tree is comprised of n-channel devices, the domino logic circuit of FIG. 1 is said to be n-channel based.
For consistency and ease of understanding, n-channel based logic is arbitrarily chosen for discussion herein. It should be understood, however, that the discussion is equally applicable to p-channel based devices, and that the apparatus and methods of the invention described herein can be readily adapted for use with p-channel based devices by those of ordinary skills in the art given this disclosure.
When CLK signal 22 goes low, the precharge phase begins. P-channel precharge device 10 is turned on, connecting output terminal 23 to Vdd. N-channel discharge device 18 is turned off, disconnecting the circuit from Vss. Output terminal 23 is pulled high, causing node 25 to go low via inverting buffer 20.
The evaluation phase occurs upon the low-high transition of CLK signal 22. When CLK signal 22 goes high, p-channel precharge device 10 is turned off, removing Vdd from the circuit. Further, n-channel device 18 is turned on by the high CLK signal 22.
During the evaluation phase, output terminal 23 either stays high or is pulled toward Vss depending on the state of the signals on conductors 24, 26, and 28. In the example of FIG. 1, if signals A-C on conductors 24, 26, and 28 are all high, a discharge path between output terminal 23 and Vss exists, causing output terminal 23 to pull low. When output terminal 23 goes low, node 25 goes high via inverting buffer 20. On the other hand, if any one of signals A-C on conductors 24, 26, or 28 is low, output terminal 23 remains disconnected from Vss and stays high, causing node 25 to stay low. As is evident from the foregoing, domino logic gate 2 of FIG. 1 implements a NAND-3 gate.
To implement more complex functions using domino logic, multiple single domino circuit stages, such as that shown in FIG. 1, are cascaded. Referring to FIG. 2, domino logic stage 2 of FIG. 1 is reproduced on the left hand side. Node 25 of domino stage 2 is used as an input to an n-channel evaluation device 30 of a subsequent domino stage 32. Domino stage 32 also has an input D on conductor 42 coupled to another n-channel device 34. During precharge, node 23 of stage 2 is pulled high by p-channel precharge device 10 as discussed earlier. Further, output terminal 36 of domino stage 32 is also pulled high by p-channel precharge device 38 when CLK signal 22 goes low. N-channel discharge devices 18 and 40 are turned off, disconnecting domino stages 2 and 32 respectively from Vss.
During evaluation, the high CLK signal 22 shuts off both p-channel precharge devices 10 and 38 and turns on both n-channel discharge devices 18 and 40. If input signal D on conductor 42 is high, n-channel device 34 conducts, causing output terminal 36 to go low and node 44 to pull high via an inverter 46. If all of inputs A, B, and C on conductors 24, 26, and 28 of domino stage 2 are high, node 25 of domino stage 2 goes high during evaluation as discussed in connection with FIG. 1. A high node 25 will cause n-channel evaluation device 30 to conduct, pulling output terminal 36 low and node 44 high. As is evident from the foregoing, cascaded domino logic stages 2 and 32 of FIG. 2 implement the Boolean function (A.B.C)+D.
Although domino logic circuits offer advantages in area and speed, there are several disadvantages. In complex circuits involving many cascaded domino gates, the capacitive loading on the common clock line, e.g. CLK signal 22, could be unacceptably high. This is due to the fact that a common clock must simultaneously clock all the stages of a given domino circuit. Furthermore, that common clock is used to control both the precharge device and the discharge device in each stage.
Another problem relates to charge redistribution. Domino logic suffers from charge redistribution because there may be enough parasitic capacitance in the serial devices of the evaluation tree, e.g. devices 10, 12, 14, 16, and 18, to cause the potential at the precharged output terminal, e.g. output terminal 23, to fall below the switching threshold although there is no actual electrical path to ground. Charge redistribution decreases the reliability of the circuitry because it may cause the output terminal to falsely switch during the evaluation phase.
Furthermore, all stages in a domino circuit must complete their evaluation before anyone stage can begin to precharge. For example, the circuit of FIG. 2 must wait until domino stage 32 completes its evaluation before stage 2 can begin to precharge. When numerous stages are cascaded with the output of each stage dependent on the result from the evaluation of a previous stage, this delay can become significant.
Thus, there exists a need for an improved CMOS circuit that can reduce the capacitive loading on the common clock line. The improved CMOS circuit preferably employs fewer devices in the evaluation tree to alleviate charge redistribution and charge sharing problems. Further, it is preferable that the improved CMOS circuit permits pipelining, i.e., the ability of different stages of a circuit to perform different tasks at different times. To improve performance, the improved CMOS circuit preferably includes circuitry to improve the noise margin and reduce the instantaneous peak current as well as power consumption.